VAX addressing

Johnny Billquist bqt at
Sat Oct 30 06:04:28 CDT 2010

On 2010-10-30 01:12, <arcarlini at> wrote:

> Johnny Billquist [bqt at] wrote:
>> >  Now, I direct you all to page 4-7 of that document, which talks about
>> >  physical addresses on a VAX.
>> >  Notice how a physical address on a VAX can be 34 bits, while the
> virtual
>> >  address is only 32 bits.
> VAX virtual addresses have always been 32-bits although system space S1
> (the top 1GiB) was never defined. The XVA project allowed it to be used
> (on some hardware platforms).

Yes. And the virtual address space is divided into 4 parts (as you well 
know :-) ). P0, P1, S0 and S1. Only P0 and P1 is actually process local, 
while S0/S1 is system wide.

> The (related) XPA project allowed the physical address space to grow
> beyond
> 1GiB but only to 4GiB (32-bits).

Well, the design allows it to grow to 34 bits. Specific implementations 
might have limited it to 32 bits, but that's another story.

> DEC STD-032 does allow for a 34-bit PA implementation but I don't know
> of
> one. The VAX 6000/7000/10000 all only implemented 32-bit PA mode
> (afaik).
> I don't know (off hand) whether the chipset could do more.

Two different things here. The NVAX chip have two different formats of 
the page address. 21 bits or 25 bits. With 21 bits, you can only get 30 
bit physical addresses (the old VAX model). With 25 bits, you get a 
total of 34 bits of physical address. Now, I don't know if the NVAX 
brought all 34 address bits out of the chip, but that is the size of the 
physical address created by the MMU anyway.

The actual machines, such as the VAX 7000 on the other hand, clearly 
only allowed a max of 4G. Of that, 3.5G was for physical memory, and 
0.5G was reserved as I/O space. But that is a design decision of a 
machine, and have less bearing on the architecture.
It is a question of the bus used in the machine, as well as where I/O 
adapters will be present on the bus, and so on.

I suspect all software running on a VAX7000 to always have the top two 
bits of the PFN in the PTE to always be zero. But the bits are there 
none the less.

Anyhow, even with only 3.5G of physical memory, it will be more physical 
memory than any one process can have virtual memory on the VAX, since a 
process cannot be larger than 2G (P0,P1)

> So (barring any inormation to the contrary) I think it's only a
> theoretical
> possibility:-)

Probably. It would be interesting to see the pinout of the NVAX chip, to 
see if they brought all 34 bits out on that chip. All existing VAXen 
restricted physical addresses to at most 32 bits, though.


Johnny Billquist                  || "I'm on a bus
                                   ||  on a psychedelic trip
email: bqt at             ||  Reading murder books
pdp is alive!                     ||  tryin' to stay hip" - B. Idol

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