Reproducing old machines with newer technology (Re: PDP-12 at the RICM)
bfranchuk at jetnet.ab.ca
Tue Jul 14 11:16:35 CDT 2015
On 7/14/2015 9:46 AM, Jay Jaeger wrote:
> My work has been using structural models, at the gate level, in VHDL
> (Verilog would be fine, too, of course). Individual components (for
> example, a piece of an IBM SMS card, or in my existing case, gates made
> available to student engineers that were actually individual
> gates/chunks of DTL chips) get little behavioral models. As I
> mentioned, so far what I have done is reproduce and test a 12 bit
> computer designed in an electrical engineering course on logic/computer
> design. In August I plan on publishing my experience on a website.
> I would note that I also see value in the behavioral approach, which
> really would be considerably more detailed than what you get form SimH.
> The IBM 1410 cycle-level simulator I have written is closer to what one
> might get from a behavioral model, but even that is not quite so detailed.
> Using the structural / gate level techniques, one does run into some
> issues, most of which have (or will probably have) solutions:
> 1) R/S latches composed of gates in a combinatorial loop. The problems
> this causes are several, including the latch getting folded into the
> look up tables for gates which use the signal, and issues when one
> brings such a signal out to an I/O pin to feed to a logic analyzer,
> which can cause problems to appear and disappear. My experience is that
> one can add a D flip flop after the RS latch. This typically works
> because at 50 Mhz, it adds only 20 ns delay, which is comparable to gate
> delays these old machines typically had.
> 2) One-shots. I haven't had to address this one yet, but I am sure
> that I will. I expect that one can simply use a counter to handle it -
> no big deal at all.
> 3) Flip flops which are clocked from combinatorial signals. These tend
> to cause timing/glitch issues. For example, in one case the
> combinatorial output was a zero-check on a counter. Since the counter
> flip flops did not all change at exactly the same time, that signal
> could glitch during the simulated machines master clock edge. They
> respond well to the same general solution as #1 - stick a D flip flop
> between the combinatorial output and the clock input. In the case I
> mentioned, that gave the signal an entire 50 Mhz clock period to settle
> And of course, getting the detailed information one needs to develop
> such a model can be a challenge. Fortunately for the older IBM
> machines, IBM produced ALDs - Automated Logic Diagrams - which I hope
> will generally have enough information.
> My experience on FPGA forums during the development of my 12 bit
> computer implementation was mixed. I got some helpful comments, but the
> majority of folks were not helpful, and instead preferred to bash me for
> not redoing the entire machine design using FPGA's the way these
> particular folks felt was "the only right way" to use them. Bah.
I have felt the right way is NOT to use VHDL or VERLOG sadly. I use
altera and using AHDL is the best for me as it cleanest language so far.
FPGA's have never been standard logic, so why force standards, if you
can not even agree on gates latches and flipflops in fpgas.
Here is the link you have been waiting for, IBM 1130 in FPGA and in the
PS: Don't use blog format for the web site, they are a pain to read
or search if what you want is more than few years old.
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