Qbus split I&D?
captainkirk359 at gmail.com
Mon Mar 16 22:10:25 CDT 2015
On 16 March 2015 at 20:40, Paul Koning <paulkoning at comcast.net> wrote:
> Interesting notion. With a fairly large FPGA, you could use the on-chip memory for a single-chip solution (well, not quite, some bus driver (level shifters) are likely to be needed). Or a small FPGA plus one or two SRAM chips.
You could also make use of some of those rather quite interesting MRAM
memory chip technology that's about. All the non-volatility of core,
with all the speed, low-profile, and low power consumption of modern
volatile RAM technologies.
Unfortunately, the cost of MRAM chips is rather a lot, especially
since you can't just order small batches. Minimum order on Mouser was
128 chips at something like $20 CAD per.
Christian M. Gauger-Cosgrove
Contact information available upon request.
More information about the cctalk