dave.g4ugm at gmail.com
Fri Oct 23 03:27:15 CDT 2015
> > And if you are going to learn an FPGA development language look at
> > SystemVerilog/Verilog, OpenCL, or VHDL. Certainly not AHDL. It was bad
> > even when it was new. It does not get better with age.
> I'll go back to schematic entry before I touch them.
> They FUCK!
Please keep profanity off the list.
You can continue to use AHDL but just like any lower level language, its proprietary to the Altera tool chain, may need work to move between chip families, and means you will have to do almost all the work yourself. There is very little AHDL code available for download. So you are cutting yourself off from the rest of the world where the formally standardized tools VHDL and Verilog have largely taken over from proprietary languages like AHDL.
I was going to say that there is no "parameter passing" in VHDL. You define an entity and then connect it to a higher level entity, but looking in the help this isn't true. I also struggled with this when I was building a "Baby Baby" as I wanted to have different types of output device and have conditional synthesis but this does not appear to be supported.
> > Don
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