M8192 KDJ11-A ZKDJB2 XXDP Test Failure
cube1 at charter.net
Mon Sep 14 07:50:54 CDT 2015
I have fiche for ZKDJB0, and fortunately it seems to match at this
particular error and address.
"This test looks for BEVENT to Interrupt when BIT 6 in the BEVENT
Control register is set and interrupt priority level is set to 5".
The particular error that you identify occurs as the result of an EMT
trap anywhere during the test. However, the most likely error would be
that the BEVENT interrupt did not occur. It would seem that the most
likely cause is that you have not configured the LTC clock interrupt -
but I am on my way out the door so I don't have time to look at the
KDJ11 manual to confirm this.
You can bypass this test by setting bit 10 of the XXDP switch register
to 1. This is something you don in XXDP *before* you start the test
program (before you enter the "R" command).
On 9/14/2015 4:40 AM, Holm Tiffe wrote:
> While checking my repaired KDJ11-A M8192 Board with xxdp I get
> the following error:
> BOOTING UP XXDP-XM EXTENDED MONITOR
> XXDP-XM EXTENDED MONITOR - XXDP V2.5
> REVISION: F0
> BOOTED FROM DL3
> 124KW OF MEMORY
> NON-UNIBUS SYSTEM
> RESTART ADDRESS: 152000
> TYPE "H" FOR HELP !
> .R ZKDJB2.BIC
> ERROR WHILE TESTING BOARD FUNCTIONS
> ERROR # =001166
> ERROR PC =040662
> The Board is working flawlessly otherwise.
> Can please someone with such a CPU can do a similar test and what does this
> error mean? I get this error with two different J11 Chips.
> In the Docs
> ( http://bitsavers.trailing-edge.com/pdf/dec/pdp11/xxdp/PDP11_DiagnosticHandbook_1988.pdf)
> is shown thatthe test should ask for a Switch Register setting, in my case
> it doesn't. Is the test defective?
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