CDC 6600/Cyber 73 Memories - WAS: Harris H800 Computer

Paul Koning paulkoning at
Thu Apr 21 15:36:55 CDT 2016

> On Apr 21, 2016, at 3:55 PM, Chuck Guzis <cclist at> wrote:
> ...
> Ten was a number that figured into various aspects.  The clock was
> nomially 10 MHz;

In serial numbers 1-7 only nominally -- the clock was a ring oscillator, tuned by tweaking wire lengths.  Starting with serial number 8, there's a crystal oscillator (in the ECS controller if ECS is present, otherwise in the CPU).

> ...
> Initially, the maximum central memory size was 131KW; late in the
> series, a 262KW option was added, necessitating extensive code changes,

I thought the 70 series (6000 series) was 131 kW max because the top bit is the "ECS active" bit.  170 series makes it 262k.
> ...
> For a couple of years, I worked on the development a system using up to
> 4 CPUs with a common 4MW of bulk core (ECS).  Since ECS transfers, after
> an initial startup overhead ran at full memory speed, a model was
> contrived that divided programs up into modules to create "chains", with
> inter-module communication, each module resident in either ECS or in a
> CPU. 

Neat.  PLATO made extensive use of ECS, swapping per-terminal state and programs in and out of ECS for fast interactive service.  ECS was also where most I/O buffers went, with PPUs doing disk and terminal I/O from/to ECS rather than central memory.  A dual mainframe 6500 system (4 "unified" processors total) did a decent job supporting 600 concurrent logged-in terminals, out of a total of 1008 connected.  That was around 1977 when I worked on that system at the U of Illinois.


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