MEM11 update

Guy Sotomayor ggs at
Mon Feb 8 12:09:53 CST 2016

Just wanted to let folks know where I am with respect to the MEM11 project.

I had decided to take a break from writing J1 code and updating the simulator to actually work on
the hardware.

To make things easy for myself, I decided to use my FPGA eval board and build a daughter board
with CPLDs and other parts (FRAMs, etc) so that I could have another vehicle for validating the J1
code.  This should also be a fairly simple board to build and I could focus on functionality (and test
points) rather than trying to make it fit into an SPC form factor.

I wrote a lot of the Verilog code for the CPLDs and quickly found out that my partitioning wouldn’t
fit in any reasonably sized CPLDs.  Even with some additional re-partitioning, it was touchy as to
if it would fit (changing a couple of lines of Verilog code caused the design to no longer fit).

I went back and thought about the problem and decided that the easiest thing to do would be to
create a non-SPC formfactor board that was SW & HW functionally correct.  So, I’ve been working
on writing all of the code to fit in an FPGA.  One advantage is that I could re-use a lot of the code
that I wrote for the CPLDs.

Last night I managed to get a reasonably clean synthesis of the design.  The only thing missing is
the UNIBUS code (which I hadn’t written yet).  It fits easily into the FPGA that I’ve chosen (a Xilinx
Spartan 3-E 500).

By going this route, I’ve discovered some incorrect assumptions that I’ve made in terms of how the
HW will appear to the J1 code.  So I have to update the simulator to match this and the relevant J1

So, things are moving forward.  I also wanted to get folk's opinion on the need to actually produce
an SBC form factor board.  In other words (and sort of in line with how peripherals were done on the
original 11/20) is it OK to have the MEM11 be outside of the 11/20 chassis and connect via BC11A
(my replica) cables?

I wanted to put that out, because it may require a fair amount of work to make everything fit into an
SPC form factor.  That’s assuming of course that the power requirements for the MEM11 can be
fulfilled by a single SPC slot.  One of the things that I can do with the “prototype” is actually measure
the incoming power.  I’m hoping that it will but in the worst case, it may require splitting the MEM11
functionality across multiple boards.

TTFN - Guy

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