Reproduction micros

Noel Chiappa jnc at
Tue Jul 19 11:10:02 CDT 2016

    > From: Paul Koning

    > The article, as usual, talks about a whole bunch of things that are
    > much older than the author seems to know.

"The two most common things in the universe are hydrogen and stupidity." OK,
so technically it's ignorance, not stupidity, but in my book it's stupid to
not know when one's ignorant.

    > RISC, as a term, may come from IBM, but the concept goes back at least
    > as far as the CDC 6000 series.

Hmm; perhaps. I always felt that RISC meant 'making the basic cycle time as
fast as possible by finding the longest path through the logic - i.e. the
limiting factor on the cycle time - and removing it (thereby making the
instruction set less rich); then repeat'. (And there's also an aspect of
moving complexity from the hardware to the compiler - i.e. optimizing system
performance across the _entire_ system, not just across a limited subset like
the hardware only).

As I've previously discussed, RISC only makes (system-wide) sense in an
environment in which memory bandwidth is plentiful (so that having programs
contain more, simpler instructions make sense) - does that apply to the CDC

    > Pipelining, to the CDC 7600.

Didn't STRETCH have pipelining? Too busy/lazy to check...

    > And if you equate RISC to load/store with simple regular instruction
    > patterns, you can probably go all the way back to the earliest
    > computers

Well, I'm not at all sure that load-store is a good indicator for RISC - note
that that the PDP-10 is load-store... But anyway, moving on.

One of the books about Turing argues that the ACE can be seen as a RISC
machine (it's not just that it's load-store; its overall architectural
philosophy is all about maximizing instruction rates).


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