Reproduction micros

Liam Proven lproven at
Thu Jul 21 07:38:05 CDT 2016

On 20 July 2016 at 21:29, Paul Koning <paulkoning at> wrote:
> I don't remember the earlier ARM designs, but it was my impression that DEC's StrongARM was the one that made really large strides in low power (especially power per MHz of clock speed).  Interestingly enough, StrongARM was one of the few (and the first?) independent designs; it used the ARM architecture specification but not the actual logic design as others did.

Hmm. That wasn't my impression at the time, no.

The big deal with StrongARM was that it had a dramatically increased
speed -- whereas Acorn ARMs ran from 8MHz in my original Archimedes
A305 to 12MHz for the first SoC ones (A3010 with ARM 250) to 25MHz for
the ARM3-powered A5000, Digital's first StrongARM ran at 100-200MHz.
To keep the core fed with data at this ridiculous speed,  it had
onboard L1 instruction & data caches.

Original PR:

Self-modifying code could write back to and thus run from the cache
before it was propagated to the main RAM, which meant that some RISC
OS code had to be rewritten.


The "Kinetic" StrongARM upgrade for the RISC PC therefore had RAM on
the CPU daughterboard, as the motherboard RAM was not even close to
fast enough.

So at least in the marketing to the Acorn user community, no, power
draw wasn't even mentioned. It never came up. The original ARMs were
low-power, and so was StrongARM.

StrongARM wasn't a big win for the Newton, inasmuch as the Original
MessagePad (OMP) had an ARM610 in it. The Newton 2000 was the first
model with a StrongARM but it was merely an upgraded CPU for the newer

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