Guy Sotomayor Jr
ggs at shiresoft.com
Thu Jul 21 22:34:57 CDT 2016
> On Jul 21, 2016, at 6:53 PM, ben <bfranchuk at jetnet.ab.ca> wrote:
> On 7/20/2016 10:42 AM, Pete Turnbull wrote:
>> On 20/07/2016 16:44, Paul Koning wrote:
>>> It is true that a few RISC architectures are not very scrutable.
>>> Itanium is a notorious example, as are some VLIW machines. But many
>>> RISC machines are much more sane. MIPS and ARM certainly are no
>>> problem for any competent assembly language programmer.
>> Indeed. I've written a modest amount of assembly language code for
>> MIPS, and a bit more for ARM, and I didn't find either at all
>> inscrutable. Yes, be aware of pipelining and branches and so on, but
>> it's not hard.
> But alas , they seem to change cache and pipeline with every cpu
> starting with 386. How can one write effective programs for large
> data memory access, with out this knowledge?
You read the Intel Optimization Guide.
TTFN - Guy
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