Reproduction micros

Chuck Guzis cclist at
Fri Jul 22 13:59:59 CDT 2016

On 07/21/2016 11:34 PM, Lars Brinkhoff wrote:

> It's not.  Peter is talking about a four-bit field in the
> instructions. You're talking about a six-bit field in the program
> counter.

Something that's always bothered me about three-address architectures
like ARM is why there is the insistence on that scheduling bottleneck,
the condition code register?  You can see how two-address architectures
like the x80 and x86 try to get around the problem by having certain
instructions not modify certain condition code bits and even have
specialized instructions, such as JCXZ, that don't reply on a specific
condition code.

Anyone have a clue?


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