How do they make Verilog code for unknown ICs?

Guy Sotomayor Jr ggs at
Mon Jun 20 16:06:26 CDT 2016

> On Jun 20, 2016, at 1:56 PM, Swift Griggs <swiftgriggs at> wrote:
> On Mon, 20 Jun 2016, Paul Koning wrote:
>> used to how C or similar languages work.  For example, in this C code:
>> 	a = 1;
>> 	b = a;
>> a and b will both equal 1 at the end.  But in the VHDL code:
>> 	a <= 1;
>> 	b <= a;
> Whoa. That makes total sense, though. In the real world, I'm guessing the 
> "less than" just reflects that a signal might not have the level you 
> expect.

The best way to think about the two different assignment operators (<= is an
assignment *not* less-than-or-equal) is that one happens “now” and the other
is resolved on clock edges.

So assuming that a & b are 1 bit wide and that initially both a and b are 0 (or
in verilog terms 1b0).

In the first example, both a and b will be 1b1.  In the second example, at the end
of the first clock cycle, a will be 1b1 and b will be 1b0.  At the end of the next
clock cycle, a will be 1b1 and b will be 1b1 also.

TTFN - Guy

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