CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?
cclist at sydex.com
Tue Jun 21 11:17:41 CDT 2016
On 06/21/2016 08:47 AM, dwight wrote:
> I would say that the most important part of either language is the
> ability to describe the time of simultaneous events. This is unlike
> most programs written in C or such. Of course, one can write a
> simulation language in C.
I tend to think of Verilog/VHDL/SystemC as being first cousins to the
much older event simulation languages, Simscript Simula and GPSS. I
believe that in the early days of LSI, one or more of them were actually
used in the design process.
If you've used any of the aforementioned simulation languages, then
transitioning to VHDL/Verilog is much easier.
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