CDC 6600 emulation - was Re: How do they make Verilog code for unknown ICs?

Paul Koning paulkoning at
Wed Jun 22 11:01:56 CDT 2016

> On Jun 22, 2016, at 9:15 AM, Noel Chiappa <jnc at> wrote:
>> From: Dwight Kelvey
>> The RIS[C]/CISC is really not even relevant in todays processors since
>> the main limiting factor is memory access bandwidth and effective use
>> of caches.
> Memory bandwidth has often been the limiting factor over the complete
> timeline of CPU's/systems. (It would be interesting to draw up a timeline,
> showing the periods when it was, and was not.) Yes, caches can help a lot,
> but inevitably they will miss (depending on the application, more or less
> often).

I can't think of an obvious example where memory speed wasn't a concern.  Possibly a reason is that memory would be tailored to the rest of the system (cheaper lower cost core if the CPU didn't need it faster).  But, for example, making the memory run well is a large part of why the 6600 looks the way it does.

> The RISC/CISC thing actually is kind of relevant to this, because RISC
> focuses on getting the CPU cycles to be as fast as possible, and that kind of
> implies simpler instructions --> more instructions to get a particular task
> done.

One consideration is that a RISC CPU requires vastly less silicon.  So you can do RISC in very small/cheap chips, or on a larger chip spend far less on the CPU core and leave more room (at constant die cost) for other stuff like caches or auxiliary components.  One place you can see this is in the various MIPS or ARM based "system on a chip" products, which have some CPU cores plus memory controllers, cache, UARTs, I/O buses, flash interfaces, crypto cores, RAID coprocessor cores, etc. etc.  Or you might find chips with very large core counts, like the Tilera 100-core processors.  (For that matter, the DECmpp many-core machine was a RISC machine for the same reason.)


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