options for replacing failed small ROMs in PDP-11
north at alum.mit.edu
Fri Jun 24 23:11:48 CDT 2016
On 6/24/2016 7:41 PM, Fritz Mueller wrote:
> On 06/24/2016 06:28 PM, Don North wrote:
>> Almost 100% certainty the part already there is a small bipolar TTL PROM.
>> What would you think it otherwise might be?
>> For a lot of these logic replacement applications DEC used the open collector
>> version, but it might be tristate variation. Check schematic.
>> Also, the microcycle on the 11/45 (and 11/70 for that matter, basically the
>> same design) is 150ns, not 30ns.
>> There are various clock timing pulses (tp1, tp2, etc) but the datapath /
>> control unit microcycle is 150ns.
> Thanks for the info, Don -- learning a lot about this stuff as I go...
> I had wondered if the part might have been a mask ROM rather than a PROM. And
> wrt. timing, I was certainly mistaken to call the nominal interval between the
> clock pulses a microcycle.
> So after staring at the flows and prints a little more closely, it looks to me
> now like the IR will be latched at FET.10 t6 (which is really IRD.00 t1?) then
> there is the rest of intervening IRD.00 during which time control signals can
> propagate to and through decode logic and the subsidiary ROM and ALU, then the
> ALU results are latched into the shifter at EXC.80 t2 or EXC.90 t2. So that's
> a solid 150ns there minimally?
> From the prints, it looks like this is an open-collector part -- I don't see
> it called out, but the chip select is wired active and I can't see that the
> outputs have any other drivers.
> So that's good news for repairing my board! Which brings on the next
> question: do folks here have a recommendation for a good programmer to try and
> track down on eBay for programming these sorts of parts?
Device E74 on GRAA is a 32x8 bipolar PROM and there are no pullups on any
outputs, so it is a tri-state device. The outputs directly drive the inputs of
several TTL logic gates.
Even if it were a mask ROM (not likely in that timeframe for that size device
and in the volume DEC would have used it) the timing would still not be that
different from a fusible link PROM. Access time would be in the 25ns to 50ns range.
The 11/45 timing generator has five timing pulses TP1 thru TP5; each one in
sequence at 30ns intervals, 150ns from TP1 to next TP1. In the flows they use
nomenclature of TP1 thru TP6, and as you indicate TP6 is really the next TP1.
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