henk.gooijen at hotmail.com
Sat Mar 5 10:44:59 CST 2016
From: Noel Chiappa
Sent: Saturday, March 05, 2016 2:01 PM
To: cctalk at classiccmp.org
Cc: jnc at mercury.lcs.mit.edu
Subject: Re: QSIC update
> So here's a quick update on where Dave Bridgham and I are with the
> QSIC ... We have the first of two wire-wrap prototype QBUS
> more or less (see below) done .. the hardware is 'mostly' working;
> of the work from here on out will be FPGA, etc, programming. There
> _are_ a few additional QBUS lines used for bus master (DMA) and
> interrupts which we haven't used yet, and one of the first things done
> now is to get those two kind of bus cycles working
> With that in hand, we can do the first controller (RK11), using memory
> in the FPGA to simulate a small disk.
Well, Dave has made a big step down that road; he has DMA working (both the
bus arbitration cycle for DMA, as well as master-mode transfers to and from
QBUS slave memory).
He's now starting in on interrupt cycles; once those work, he effectively
emulation of a minimal small RK (he already has all the registers, since he
needs them to control the DMA to and from the RAM disk). At that point I
should be able to test it by making it the swap drive on a Unix V6 load.
sounds very good - nice progress!
When you get to it, that will be a fast swap drive ;-)
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