pontus at Update.UU.SE
Wed Sep 7 01:51:34 CDT 2016
On Wed, Sep 07, 2016 at 01:58:24AM -0400, Ethan Dicks wrote:
> On Tue, Sep 6, 2016 at 12:11 PM, Marc Howard <cramcram at gmail.com> wrote:
> > It seems to me that one possible solution would be to whip up a PLL in a
> > CPLD or FPGA to generate 12 sector timing from a 16 sector pack or vice
> > versa.
> This is one of the recurring conversations here - 12-sector packs are
> abundant compared to 16-sector packs, and the only difference is the
> slits in the hub and the consequent formatting on the matching
I do recall discussion of manufacturing new hubs but not the outcome. I
imagine that someone with access to a lathe and mill would be able to
make new hubs with good enough tolerances.
Is there some caveat to doing this (besides finding someone with a lathe
More information about the cctalk