Which Dec Emulation is the MOST useful and Versatile?
robert.jarratt at ntlworld.com
Fri Oct 27 12:47:55 CDT 2017
> -----Original Message-----
> From: cctalk [mailto:cctalk-bounces at classiccmp.org] On Behalf Of Paul
> via cctalk
> Sent: 27 October 2017 18:28
> To: Dave Wade <dave.g4ugm at gmail.com>; General Discussion: On-Topic and
> Off-Topic Posts <cctalk at classiccmp.org>
> Subject: Re: Which Dec Emulation is the MOST useful and Versatile?
> > On Oct 27, 2017, at 4:54 AM, Dave Wade via cctalk
<cctalk at classiccmp.org>
> > Kip,
> > I think "emulation" and "simulation" get used pretty much
> > SIMH is touted a simulator, Hercules/390 as an emulator yet they are
> > both programs that provide a "bare metal" machine via software on
> > which an operating system can be installed. Neither make any attempt
> > to reproduce the speed of the original CPU.
> True. And by some argument, an FPGA implementation (from an HDL
> behavioral model) is also a software implementation, just written in a
> programming language.
> Recently I commented to an old colleague that there are many different
> of emulation possible, and any one of those may make sense -- it's just a
> question of what you're after. So you can emulate in a conventional
> programming language, as SIMH does, reproducing the programmer-visible
> behavior of the machine but not its timing. Bugs from the original might
> appear if those bugs are known to be important, but probably not
> This kind is (nowadays) likely to run faster than the original; certainly
> usually mimic the original timing, neither for computation nor I/O.
> You can make timing-accurate software emulators, with lots of work. SIMH,
> paced mode, and provided the I/O waits are reasonably accurately expressed
> units of machine cycles, isn't quite timing accurate but is somewhat
> You can build a behavioral simulator (SIMH style, basically) in an FPGA.
> isn't necessarily any more capable or accurate than a software simulator.
> 2011 is an example I know of, and I've see articles about other PDP
> of this kind. Since the design is new, created from a behavioral
> (data book, functional spec, architecture spec) it will be about as
> You can also, if the data exists, build a lower level (gate level or
> FPGA model. Given schematics and wire lists, it should be possible to
> implementation that's an exact copy of how the original machine worked
> (assuming of course the documentation is accurate, which is not
> case). Such an emulation would replicate strange and undocumented
> of the original -- and allow you to find out where that came from. I've
> working on such a thing for the CDC 6600, which is surprisingly hard given
> the design lives right on the hairy edge of not working at all
timing-wise. But it
> does accuarately model the peripheral processors right now, and indeed it
> shows and explains some undocumented oddities that are part of that
> machine's folklore.
> So it's a question of what you're after. If you want to run the software,
> the machine at the programmer level, SIMH or equivalent is quite adequate.
> you want to teach FPGA skills, an FPGA behavioral model emulation is a
> project, especially for a small machine like a PDP-8. As for the gate
> model, I'm not sure what argument to make for that other than "paul is a
> crazy" and "because the data exists to do it". :-)
If I had the skill, data and time, I would always go for a gate level model.
However, I do most (sim/em)ulation in SIMH instead, like I have been doing
for MU5 where I lack the data and the time and probably the skill as well,
but I can always acquire the skill, the other two are harder to find.
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