Which Dec Emulation is the MOST useful and Versatile?

Al Kossow aek at bitsavers.org
Fri Oct 27 15:39:23 CDT 2017

On 10/27/17 12:57 PM, Paul Koning wrote:

> That doesn't sound even close.



While computers now are composed by many integrated circuits containing each millions of logical units,
processing data with a speed of a few gigabits per second in a parallel-flow of 64 bits,
the USSC's CPU-logic was composed of over 1000 circuit boards with each only a few active components.
One circuitboard contained only 4 simple logical units, the ferractors.
These circuit-boards processed the data with the theoretical speed of 700 KBits/second.
The ferractors were tiny transformers, performing one-bit operations, powered by 700 KCs AC.

On the positive half of the cycle, the ferractor-core was magnetised or not depending on the current through the bias-coil,
which made the total magnetic field in the core to exceed the hysteresis-threshold or not.
In the subsequent negative half-cycle the ferractor showed on the secondairy coil a high or a low impedance,  depending
on whether it had been magnetised or not.
On low-impedance a positif bias-current was generated for the next ferractor-circuit.

Since each ferractor was set in one cycle-half and was read in the next cycle-half, an one bit-stream of a register was
by 24 ferractors in series, alternatingly fed by opposite phases.
In such a string of ferractor-circuits 12 bits cycled around, 10 bits, a sign and a space.
The information in the registers was circling around in 4 parallel one-bit-strings.
The data in the registers cycled around with the same speed as the information on the drum-memory.

The 200 diode-boards were used in OR and in NAND functions, depending on being located in the positive-phase-circuitry
or the negative-one.
The bias-coil was connected in positive or negative polarity to enforce or to diminish magnetisation during the first
in order to create normal or inverting logical gates.

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