Which Dec Emulation is the MOST useful and Versatile?

Phil Blundell pb at pbcl.net
Fri Oct 27 16:00:59 CDT 2017

On Fri, 2017-10-27 at 13:38 -0700, Brent Hilpert via cctalk wrote:
> I wonder if they were just trying to draw an analogy between the
> inherent dynamic operation requirements of magnetic logic and the
> dynamic operation requirements of some (many?) NMOS designs (not
> really inherent to NMOS).

On the subject of NMOS dynamic logic, someone recently pointed out a
paragraph in the technical manual for a 1990s ARM2-based computer which
warned of dire consequences, including possibly destruction of the
chipset, if the circuitry was left powered with the clock stopped for
more than a second or two.

Obviously if the clock is stopped for more than a few hundred
microseconds then the logic will start to lose its marbles and the
system will need a reset to recover.  But I don't think I've previously
heard any suggestion that dynamic logic ICs would actually be damaged
or destroyed under these circumstances.  I can just about imagine that
there might be some situation where an invalid internal state would
result in a short circuit between power and ground, but that's just
supposition really.  Anybody know of a case where something bad has
actually happened?


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