Which Dec Emulation is the MOST useful and Versatile?
allisonportable at gmail.com
Tue Oct 31 16:59:24 CDT 2017
On 10/30/2017 12:43 PM, Paul Koning via cctalk wrote:
>> On Oct 27, 2017, at 5:00 PM, Phil Blundell via cctalk <cctalk at classiccmp.org> wrote:
>> On Fri, 2017-10-27 at 13:38 -0700, Brent Hilpert via cctalk wrote:
>>> I wonder if they were just trying to draw an analogy between the
>>> inherent dynamic operation requirements of magnetic logic and the
>>> dynamic operation requirements of some (many?) NMOS designs (not
>>> really inherent to NMOS).
>> On the subject of NMOS dynamic logic, someone recently pointed out a
>> paragraph in the technical manual for a 1990s ARM2-based computer which
>> warned of dire consequences, including possibly destruction of the
>> chipset, if the circuitry was left powered with the clock stopped for
>> more than a second or two.
>> Obviously if the clock is stopped for more than a few hundred
>> microseconds then the logic will start to lose its marbles and the
>> system will need a reset to recover. But I don't think I've previously
>> heard any suggestion that dynamic logic ICs would actually be damaged
>> or destroyed under these circumstances. I can just about imagine that
>> there might be some situation where an invalid internal state would
>> result in a short circuit between power and ground, but that's just
>> supposition really. Anybody know of a case where something bad has
>> actually happened?
> I don't understand this at all. "Dynamic logic" is not a familiar concept, and certainly the NMOS logic I know isn't dynamic. Memory (DRAM) is dynamic, and will forget if you don't refresh it. But DRAM doesn't mind if you stop the clock, it just won't remember its data.
> So I don't know how you might have a logic design that "loses its marbles" if you stop the clock. And anything that is fried by clock loss is, in my view, the work of someone who should not be allowed anywhere near a EE shop.
NMOS dynamic logic relies on two things memory or register cells that
operate just like
Dram so they forget without refresh. It also relies on logic nodes that
precharge to some
state and are selectively discharged by the logic. Doing that saves
resistive pullups or
complementary logic. This type of logic has a specified minimum clock
could usually go far slower. The 8080 was an early example.
> Incidentally, while "soft core" magnetic logic is dynamic, memory core logic is not. You could slow that down and it would still work. The signals are pulses, not levels, but the pulses will still happen with a 1 Hz clock.
The timing of the logic in some cases where tied to the switching time
of the cores used. Otherwise
it was hard to determine when and if the core switched.
However rope core and ferro-transformers would work at any rate so long
as the pulse waveform was
had the right rise and fall times. FYI rope core was basically many
transformers either with a wire
in for the bit or wire around for the not bit. The cores for rope
didn't change magnetic state like
coincident current cores of the bistable type as that allowed read write
but was DRO (destructive
read out with re-write) which is the more familiar core and why it had a
shorter read time and a
longer cycle time between reads.
Both have a fair amount of documentation out there. The
ferro-transformer logic were documented
well too but you have to hunt for info. They also came in many forms as
to the logic performed
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