QSIC update and request
dab at froghouse.org
Mon Jan 1 14:42:34 CST 2018
Even though I've been quiet, I have been making slow progress on the
QSIC in the background. For those who've forgotten what the QSIC
project is about, here's the description:
We've been working away on getting communications with the SD card
working and that's basically there now. It initializes and reads and
writes blocks. I've also connected it through an async FIFO to the
minimal RK11 controller I had working before and that's mostly working.
That is, it can read and write blocks under control from the QBUS PDP-11
as if it were a real RK11/RK05. What more could you ask for?
Well, I could ask for a lot more really but that's pretty good. There's
a lot of RK11 functionality that I haven't implemented yet and all sorts
of configuration options we need to get in there. Also, there's a bug
where it sometimes scrambles data so it's not quite ready to boot and
run a real OS yet but it's getting awfully close.
Here's a picture to my test setup:
And a picture of a test of some spray-on glass frosting used as a light
diffuser on the indicator panel. In this picture you can also see the
new LEDs I found that are a much better color match to the old
incandescent bulbs than the LEDs I picked for my first attempt.
Now for the request. I've decided that I'd like to put a soft-processor
in the FPGA to handle a bunch of things (configuration duties and the
USB protocol being two of the big ones). My preference would be for
this soft-processor to be a PDP-11. Surely there's hack value in using
a PDP-11 as the I/O processor for a PDP-11 but there are practical
advantages to this as well. For one, we're already familiar with it and
have a suite of development tools. Also, I can re-arrange the I/O
devices I intend to give to this soft-11 and put them directly on the
QBUS instead and do initial development there.
I'd rather not get diverted by yet another substantial development
project so I'm looking for a decent little FPGA implementation of a
PDP-11 that I could just pick up use for this purpose. Something that's
already debugged. I'm thinking closer to an 11/04 than an 11/70 and
likely just running out of block RAM on the FPGA.
Thanks for any pointers to such an implementation and thanks to everyone
who's given support and assistance as Noel and I have poked along on
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