PDP11 I/O page memory map
paulkoning at comcast.net
Thu Mar 1 08:04:03 CST 2018
> On Mar 1, 2018, at 6:12 AM, allison via cctalk <cctalk at classiccmp.org> wrote:
> ... and the MMU also
> understands that peripherals live in that physical space be it 16/18/22
> bit memory map.
That's true when the MMU is disabled; if so it supplies 1 bits for the upper bits for page 7, and zeroes for the other pages. But if the MMU is enabled, all mapping goes through its mapping registers, and page 7 is no longer special. By software convention, kernel data page 7 is configured to point to the I/O page, but that isn't required. If you wanted to be be perverse you could map the I/O page via page 6 and confuse a whole generation of programmers.
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