PDP11 I/O page memory map
jsw at ieee.org
Fri Mar 2 01:29:34 CST 2018
> On Mar 1, 2018, at 8:54 PM, Noel Chiappa via cctalk <cctalk at classiccmp.org> wrote:
>> From: Charles Dickman
>> So if the I/O page is completely (all processor modes) unmapped is
>> there any way to recover besides a power cycle? Does the RESET
>> instruction disable the MMU?
> Interesting questions!
> The CPU manuals don't say, about the RE$ET; I just tried it on the /23 I
> happen to have next to my desktop, and yes, the RESET instruction does clear
> bit 0 of SSR0.
Typically execution of the RESET instruction in a user program is treated
as a NOP when the MMU is enabled.
What generally occurs in most OS'es is that I/O Page is mapped and unmapped dynamically
based on which mode is executing. Interrupts or user program traps cause a
context switch to kernel mode. When this occurs page registers with access
to the I/O page defined are activated. The interrupt or trap is serviced then the OS returns
to running the user mode program. At this point a switch to back to a set of page registers without
I/O mapping occurs.
There are OS'es that allow regular programs to map the I/O page, These are usually
special purpose solutions (RT11XM) or granted only to privileged users (RSX11, TSX+).
The effect of RESET to initialize the MMR0 (SSR0) register is documented in
the PDP11 Handbook 1979 or the J11 Programmers Reference. I could not find it in the
reference immediately below, much to my surprise.
Check out Chapter 1 in the KDJ11-A CPU Module User's Guide for an overview
of PDP11 memory management. This implementation was (mostly) backward compatible with
PDP-11 models having 22bit , 18bit or no memory management.
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