PDP11 I/O page memory map
jsw at ieee.org
Fri Mar 2 13:28:48 CST 2018
> On Mar 2, 2018, at 9:11 AM, Paul Koning via cctalk <cctalk at classiccmp.org> wrote:
>> On Mar 2, 2018, at 8:37 AM, Noel Chiappa via cctalk <cctalk at classiccmp.org> wrote:
>>> From: Jerry Weiss
>>> Typically execution of the RESET instruction in a user program is
>>> treated as a NOP
>> Yeah, that's not documented in most PDP-11 CPU manuals, either. It's one of
>> the things that makes the PDP-11 impossible to virtualize; only HALT and SPL
>> trap, IIRC. M[TF]P[ID] doesn't, I think, and neither does WAIT or RT[IT],
> RTI/RTT are used in the debugger, so they need to work in user mode. They refuse to raise your privilege level, though. But an RTI in user mode that returns to user mode is perfectly ok so it is valid.
> The move from/to previous are also valid, by deliberate design. This works because the previous mode is explicitly encoded in the PSW, and just like the current mode, cannot be raised by user mode RTI. It is why the kernel usually sets current == previous == user when constructing the PSW for a process.
> What does the Architecture handbook say about WAIT and RESET in non-kernel modes? I don't have mine at hand unfortunately.
In the Digital Microcomputer Processor Handbook 1979-80 edition page 280 describes the user mode restrictions on HALT, RESET. and MTPS, but nothing about WAIT.
The PDP11 Handbook 1979 does not detail user mode implications for MTPS or WAIT. HALT is called out for a trap to 10 in user mode. Prevention of a "restart" in user mode is mentioned on page 182, but nothing explicit about RESET.
As FritzM suggested, it appears there are fewer details in the PDP-11 Architecture Handbook (1983) for these instructions than these earlier references above. HALT trapping to 4 appears for later processors in the family differences section, but I did not see much else for this topic.
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