Floppy controller questions
ard at p850ug1.demon.co.uk
Tue Aug 23 17:22:07 CDT 2005
> >> Write clock sets the write data rate and should corrospond to the
> >> rate needed for media. Writeclock is 2x data rate.
> >Does this apply to both FM and MFM? The datasheet suggests a 500kHz WrClk for
> >FM and 1MHz for MFM mode, which would give a 250kHz FM data rate and a 500kHz
> >MFM data rate. Is that right?
> They are right. MFM requres twice the clock of FM as it's twice the speed.
> Obvious to me. However the statement is valid as the APPLIED clock is 2X
> the DATA rate for any mode.
> One of the confusing issues the fact that when going to MFM (AKA Double Density)
> you will always run the clock twice that of FM but the ratios of Wclock to data
> rate is always 2. The MFM pin can be used to select Wclock or Wclock/2 for
> MFM/FM operation on write and for read it can select clock or other timing
> dependent control for the read_data and read_data_window recovery.
> Oh and BTW: those specified data rates would be for 8" drives. For 5.25
> they are half that.
Unlesss you are using HD drives and disks. Those use the same data rates
Also be aware that many HD-capcable 5.25" drives turn at 360 rpm all the
time. Which means the data rate if you put a DD (or for that matter an
SD) disk in them is 6/5 times what you'd get with that disk in a DD drive
(which turns at 300 rpm). You may well need to provide a suitable clock
for 300 kbps, for example.
> >> Using a 765 for _all_ data rates and both 3.5"/5.25"/8" floppy interfaces
> >> implemented with LSttl fills a S100 board completly.
> >That's why SPLDs (GALs) and CPLDs were invented I guess. Squish the address
I always thought they were invented to make my job more painful than it
should be ;-)
> >decoder, interface logic, and the data separator into a few LSTTLs and GALs,
> >or just throw everything into a single CPLD :)
> Yep, helped design and test a mask programmed gate array that reduced the
> minimal base PC from about 15 chips to less than 7 while keeping a good
> data sep and write precomp logic.
Perhaps I've been lucky, but I've never seen that sort of desing in any
PC I've had the pleasure of working on. I've seen the more modern
single-chip disk controllers which contain a 765 'core' and the rest of
the logic in a single chip. I've seen a real 765 + one of the single-chip
data separators. And I've seen a board of logic (the original IBM
controller, for example). But I've never seen a real 765 linked to an
ASIC that contains the data seprator.
> >> Most designs implemented a subset for 8" or 5.25"/3.5" only
> >> (jumper selected) with much lower parts cost.
> >That's what I wanted. I don't have any 8" drives, so adding support for them
> >is pointless. Ideally, I want a board that has a 6502-type interface on one
> >side and a 34-pin IDC connector on the other, with support for most common FM
> >and MFM 3.5" and 5.25" formats.
> Well the interface for 3.5 and 5.25 are nearly identical and that made most
> of that simple. the only real differnce is you will likely run twice the clock
> rates for 3.5" drive than 5.25".
Unless you are using the original Sony 3.5" drives, which turn at 600
rpm, and thus use twice the data rate you might expect, 5.25" drives and
3.5£ drives use the same data rates for the same modes.
HD disks (1.2Mbyte, 1.44Mbyte respectively) in their approriate drives
use the same data rates as 8". SD and DD disks are half of those rates
_apart from the 360rpm issue I mentioned above).
FWIW, 3" are the same as those too (there never was a HD 3" disk AFAIK).
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