Floppy controller questions
ajp166 at bellatlantic.net
Tue Aug 23 10:56:36 CDT 2005
>Subject: Floppy controller questions
> From: Philip Pemberton <philpem at dsl.pipex.com>
> Date: Tue, 23 Aug 2005 14:19:52 +0100
> To: cctalk at classiccmp.org
> I've been reading through the uPD765, R6765 and 8272 FDC datasheets. All of
>them seem to cover the basics pretty well, but I've got a few quick questions
>for anyone who's used a 765-type FDC (or any other FDC that behaves in a
>similar way), or who knows a bit about floppy drive technology:
> 1) How do you vary the read/write data rate? Some 3.5" formats use MFM at
>250kbits/sec, others use MFM at 500kbits/sec. What relation does the WRITECLK
>input have to the data rate of the MFM-coded signal at the WRITE DATA output?
>What about the 8MHz master clock?
BY prescaling the clock. Master clock drive the internal cpu and
after prescaling the various timers (step rate, Head load time,
head unload time) Possible useful rates for Clock is 8 and 4mhz.
Use 8MHZ for fastest step rates, 4mhz for those drives (like sa400)
that need really slow step rates. Also the rate that the master
status register is updated is affected due to internal microprocessors
Write clock sets the write data rate and should corrospond to the
rate needed for media. Writeclock is 2x data rate. The master clock
is not synchronous to the write clock though it's easiest to derive
both from the same master source.
NOTE: like the 179x/177X basic controllers the 765 requires external logic
to scale clock rates, write clock rates demux the various drive interface
lines and generate the correct levels for driving the disk drive. Additonally
the logic does things like Data Clock recovery, Write precompensation timing
as those functions required logic faster than was doable in NMOS in 1981.
The second generation chips such as 9266 and later WD37C65 integrated
most of that logic into the chip in the AT-PC style (subset of full capability).
Using a 765 for _all_ data rates and both 3.5"/5.25"/8" floppy interfaces
implemented with LSttl fills a S100 board completly. Compupro, IMS and others
are examples. Most designs implemented a subset for 8" or 5.25"/3.5" only
(jumper selected) with much lower parts cost. A design for 5.25/3.5 floppy
(no 5.25 1.2mb) only can be simplified further for greater parts savings.
Single sided and double sided are trivial and add nothing to the design.
The bulk of the logic is in five groups, bus interface, general clock
generation, Write logic (clocks and precomp), read logic (aka seperator)
and floppy interface.
> 1a) Can the uPD765 be made to read and write both DSDD and DSHD floppies?
>If so, how? I know the WD 177x controllers could do it if the 8MHz master
>clock was increased to 16MHz (an old trick used on Acorn A3000s). Does the
>same trick work with the 765?
Yes, it was done on the 1.2MB AT-class machines. Reminder: every PC with
rare exceptions used a 765 or a derivitive based on the 765 core.
Write clock needs to be scaled to the correct value. OR you can take
advantage of the HS lone on some drives so that the FDC can be clocked
at 500khz data rate rather than the odd (non sub-multimple of 16mhz)
600/300kHz. Some designs used a 24mhz master clock to derive 8mhz,
4mhz, 1mhz, 600khz, 500khz, 300khz, 250khz, 125khz as needed for the
correct data rates. Other timing derived from the master clock is
the timing for the precomp shift register.
> 2) How does the FDC decode the data it's been given, based on the data
>window and the data read from the disc? In FM mode I guess you'd count the
>cycles within the data window - 2 would be a 0, 4 would be a 1. But what
>would you do for MFM?
For MFM is when the transiston occurs rather than how many. Generally the
Floppy generates what is by standard expected and the FDC external logic
will regenerate data pulses and data window (data window is a read clock).
> 3) What happens when the drive's head picks up a flux transition? Does the
>the drive generate a single pulse every time the head hits a transition, or
>does the drive's RD DATA output change state?
Pulse every transistion. By standard, the singal from the Floppy is a negative
going pulse with pull up to 5V.
> 4) When writing data, I'd guess that setting WR DATA high would polarise
>the magnetic coating one way, while setting it low would polarise it the
>opposite direction. Is this how it works, or does the WR DATA line get pulsed
>to make the drive put down a flux transition?
Pulsed to cause a transistion.
FDCs are not transistion polarity selective. The critical parameter is
that there was a transistion and when it occurs. The stated FRPI (flux
reversals per inch) determine the media density and MFM uses fewer reversals
per bit than FM so the density can be higher. In the density scale the
8" SD is the lowest and the 1.44mb 3.5" highest.
There is a lot here.
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