TD100 delay line chip?
ajp166 at bellatlantic.net
Wed Aug 31 16:45:14 CDT 2005
>Subject: TD100 delay line chip?
> From: Brad Parker <brad at heeltoe.com>
> Date: Wed, 31 Aug 2005 16:02:10 -0400
> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org>
>The question about the ttl oscillator jogged my memory.
>Anyone recognize a line of "delay line" chips with names like TD25,
>TD50, TD100, etc... The look they were expensive at the time, like $10
>The TD100 pinout looks like this:
>input | 1 14 | vcc
> | 2 13 |
> | 3 12 | 20ns
>40ns | 4 11 |
> | 5 10 | 60s
>80ns | 6 9 |
>gnd | 7 8 | 100ns
>I don't have an exact part number or mfg. (I know where I can find one
>but it's not easy and will take some work)
>I want to model these in verilog but I'm not exactly sure how they work.
>They are delay lines, but I'm not sure how they react. The input seems
>to be a short pulse from high to low of about 40ns. I'm assuming this
>produces an approx 40ns pulse after the prescibed delay, but I'm not
>I would love to see a few pages from a data book which describes how
>these react (enough to model them correctly).
Treat it as if it were a transmission line with length N. The rough length
for wire is 1ns/ft but if the wire is wound around a grounded metallic form
the wire to ground acts like a transmission line and the insulation sets
the spacing hence characteristic impedence as well as velocity factor.
Allowing for velocity factor the 1ns/ft can be be more like 1.5ns/ft. So
winding 30ft of #42 wire is actually compact and a substantial delay.
I did a DL for the 16k muxed Drams that way and found I could easily
measure the delay and trim the timing very accurately. It was far
more stable than RC oneshots (74121/123/9602) it was stable too.
During testing I was using rolls of RG174 (50 ohm .125 dia coax with
a VF of .66). Turns out that even a 100ft roll was way too long.
Bulky but easy to get 15ns (about 117.3 inches) delay accuratly.
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