MITS 8800B CPU Board

Randy McLaughlin cctalk at randy482.com
Wed Jun 15 15:22:46 CDT 2005


From: "Tom Jennings" <tomj at wps.com>
Sent: Wednesday, June 15, 2005 2:51 PM


> On Tue, 14 Jun 2005, Randy McLaughlin wrote:
>
>> Please note that by using current RAM chips that are >= 64K address 
>> decoding is extremely simplified.  To carve out space from ROM not only 
>> butchers the address map but adds complexity.
>>
>> As I already said either an I/O instruction or an address line can 
>> accomplish the same task.
>
> I think you missed the point, plus I left out one detail:
>
> * It specifically doens't require carving the address space up AT
> ALL.  The machine simply has 64K contiguous RAM, from 0000h to
> ffffh.
>
> * The EPROM board used PHANTOM to disable RAM when addressed -- I
> left that little detail out!
<snip>

I understood, I was referring to the trigger for phantom.  It does not 
matter how the flip flop gets set as long as it does not interfere with the 
initialization of the monitor.

I was agreeing that it is best to use phantom to access ROM rather than 
address decoding that leaves a ROM window.  In the early days of S100 
systems mass storage was not the norm, so having a permanent ROM monitor 
(some complete OS's with assemblers, etc) made sense.  Another point is 
there were no 64K RAM chips so address decoding had a different standard to 
what anyone would build today.  Today I prefer 512K RAM's so that address 
decoding is replaced with MMU.

The methods of releasing phantom that I'm most familiar with are either a 
bit in an I/O port so the ROM can be brought back in the address space if 
needed or a particular addressing bit that shows the ROM is no longer 
needed.  Tarbell used address bit 5 to reset phantom, the boot ROM just 
falls through to disable the boot ROM.  Tarbell's boot ROM reads a sector 
into RAM and when execution hits it phantom is disabled.

There are lots of ways to reset phantom depending on needs.

With Flash ROM's I prefer I/O port access so the ROM can be re-programmed 
ala SuperIO.


Randy
www.s100-manuals.com 





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