64 pin SIMM (Mac IIFX) Specs?

Tony Duell ard at p850ug1.demon.co.uk
Mon Sep 12 17:48:19 CDT 2005


[DIm and DOut]

> Well, darn it, they aren't linked.  It turns out that the memory 

Argh!

> controller on the IIfx buffers the writes, so that the CPU can go do 
> something else after only 2 cycles instead of 6, unless, of course, 
> the next operation is a memory access.
> 
> So the the data lines from the SIMMs are routed to 74F573 D-type 
> latches.  It appears that the SIMM's DIN comes from the latches' 
> outputs and DOUT goes to the latches' inputs.   I have not confirmed 
> it yet (must pull the PGA 68030 to get access to the data lines) but 
> I suspect that the bidirectional databus goes to the input lines of 
> the latches.

I would think so. Maybe with more buffers ('F245?) or even an ASIC in 
between, but I doubt the latter.

> 
> So, on a read, the data would just come out of the memory straight to 
> the bidirectional data bus.   On a write the data bus would take data 
> to the latches' inputs where it would be buffered, and the memory 
> controller presumably has control of the LE (latch enable) and OE 
> (output enable) lines to the latches.

If the only thing that drives those DIn lines are the 'F573s, then there 
would be no need to ever tri-state the outputs. In which case you may 
well find that OE/ is tied to ground.

> 
> So, if I tied DIN and DOUT together, it looks like there are at least 
> two potential trouble spots.
> 
> 1)  If the memory controller does not switch the latches to High-Z 
> (OE inactive) upon completion of Writes, then  on a Read, the data 
> from the memory would be in contention with the data still held by 
> the latches from the previous write.

Yep. 

> 
> 2)  While the memory controller is buffering a Write, that data would 
> feed back from the latches, along the tied together In and Out to the 
> bidirectional data bus.

The outputs of those latches would then be contending with every other 
device on the bus. I think it's unlikely those latches are ever 
tri-stated in normal operation unless some other device can drive the DIn 
of the RAMs -- and what would that device be?

-tony




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