SIMM, Address Lines Order?
trag at io.com
Sun Sep 25 20:59:02 CDT 2005
When connecting DRAM chips to the pins of a SIMM (i.e. laying out the
traces) does it matter if the order of the address and data lines is
preserved? In other words, does A0 on the SIMM need to connect to A0
on the chip, and A0 on all the other chips as well? These are old
DRAM, such as FPM or EDO, used in 30 pin SIMMs. Nothing new and
fancy like SDRAM.
I believe the answer is no. But I know from experience that there
are sometimes odd scenarios that are easily overlooked, so I figured
I'd access the shared experience and knowledge here.
It's a lot easier to layout the PCB for the SIMMs, if I don't
preserve order. And it shouldn't matter, because anything that gets
stored at address X should come back out on a read to address X.
The only circumstance I can think of that could cause a problem is if
the RAM has some kind of sequential read mode where consequeutive
addresses are expected. Reading the datasheet, I don't see a mode
like that. The closest thing is a burst mode where the Row address
stays constant and a series of Column addresses are supplied, but
that should work just fine, I think.
So, any gotchas to disordering the address and data pins between the
SIMM, and the chips and from chip to chip?
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