SIMM, Address Lines Order?

Jim Battle frustum at
Mon Sep 26 10:04:27 CDT 2005

Jeff Walther wrote:

> When connecting DRAM chips to the pins of a SIMM (i.e. laying out the 
> traces) does it matter if the  order of the address and data lines is 
> preserved?  In other words, does A0 on the SIMM need to connect to A0 on 
> the chip, and A0 on all the other chips as well?  These are old DRAM, 
> such as FPM or EDO, used in 30 pin SIMMs.  Nothing new and fancy like 
> I believe the answer is no.   But I know from experience that there are 
> sometimes odd scenarios that are easily overlooked, so I figured I'd 
> access the shared experience and knowledge here.
> It's a lot easier to layout the PCB for the SIMMs, if I don't preserve 
> order.   And it shouldn't matter, because anything that gets stored at 
> address X should come back out on a read to address X.
> The only circumstance I can think of that could cause a problem is if 
> the RAM has some kind of sequential read mode where consequeutive 
> addresses are expected.  Reading the datasheet, I don't see a mode like 
> that.  The closest thing is a burst mode where the Row address stays 
> constant and a series of Column addresses are supplied, but that should 
> work just fine, I think.

Static column mode DRAMs don't care about the mapping.

Burst mode DRAMs could be a problem.  IIRC, the burst length for older DRAMs was 
two to four sequential addresses, obtained by internally accessesing consecutive 
DRAM locations without having to wiggle the address lines.  This mode was 
typically used for filling an x86 cache line.  Thus you should at least ensure 
that A0 and A1 of the SIMM get wired to A0 and A1 of the DRAM.  The others are 
free to remap.  If you know your application doesn't use this mode of operation, 
then remap any/all of the addresses.

One last thing.  There were DRAMs that used a different number of address lines 
for RAS than for CAS.  For instance, say you have a 128K bit DRAM (for instance, 
often sorted out from failing 256Kb DRAMs) arranged as 256 rows by 512 bits per 
row.  There would be 9 address lines on the DRAM, but one of the address lines 
(probably A8) would need to be distinguished and mapped consistently.

As a disclaimer, I have designed, implemented and shipped a number (10?) of DRAM 
controllers, both in TTL and in ASIC forms, but the most recent to ship was 
about 1991, so some details might have faded.

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