SIMM, Address Lines Order?
ard at p850ug1.demon.co.uk
Tue Sep 27 12:53:59 CDT 2005
> 1) The RAS only, and Hidden Refresh cycles involve a Row address
> supplied on the address lines. So, unless there's some undocumented
> requirement that these address be supplied in a particular order, I
> don't think that will cause a problem. However, I recognize that
> sometimes datasheets (and documentation in general) assume general
> knowledge about the topic. So if there is some implicit assumption
> about the addresses supplied during a refresh, I'd appreciate someone
> explaining it to me.
I've never head of such a requirement, only that all 2^n states of the
address lines are used within a certain time.
The only issue is if only some of the address lines to the RAM are used
for refresh, then you have to make sure those are kept together (but you
can scramble their order, just as you can scramble the order of the ones
not used in the refresh operation).
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