SIMM, Address Lines Order?
Dwight K. Elvey
dwight.elvey at amd.com
Tue Sep 27 15:28:29 CDT 2005
>From: ard at p850ug1.demon.co.uk
>> 1) The RAS only, and Hidden Refresh cycles involve a Row address
>> supplied on the address lines. So, unless there's some undocumented
>> requirement that these address be supplied in a particular order, I
>> don't think that will cause a problem. However, I recognize that
>> sometimes datasheets (and documentation in general) assume general
>> knowledge about the topic. So if there is some implicit assumption
>> about the addresses supplied during a refresh, I'd appreciate someone
>> explaining it to me.
>I've never head of such a requirement, only that all 2^n states of the
>address lines are used within a certain time.
>The only issue is if only some of the address lines to the RAM are used
>for refresh, then you have to make sure those are kept together (but you
>can scramble their order, just as you can scramble the order of the ones
>not used in the refresh operation).
This is what I was talking about with the A0-A6. You need
to see how many cycles are needed for refresh. This should
be in the spec. You need to determine how many address lines
are needed to complete that cycle. As an example. If it is
a 128 cycle refresh A0-A6 need to be grouped as Tony states.
If it is 256 cycle, A0-A7 need to be grouped and so on.
The cycles tells you how many addresses need to be cycled
through on a refresh to get all of the internal banks.
They always assume starting with A0 on to figure.
Between what Tony and I are saying, does it make sense??
More information about the cctech