Tristate Buffer Output if Input is High-Z?

Jeff Walther trag at
Wed Sep 28 02:56:31 CDT 2005

>Date: Tue, 27 Sep 2005 07:54:24 -0700
>From: Eric J Korpela <korpela at>
>Subject: Re: Tristate Buffer Output if Input is High-Z?

>On 9/26/05, Jeff Walther <trag at> wrote:
>>  If a tristate buffer is enabled by its control line, but the input to
>>  the buffer is at high-Z is there a typical output?
>If there is it probably varies between parts. If you need a defined output
>for tristated inputs you should pull the inputs up or down.

Thanks to everyone for all the replies.

It sounds like the tristate buffers don't do exactly what I would 
like, although I think I can make it work with more logic in front of 
the control line for the buffer.

However, doing a bit more research, it looks like what I really need 
is a Transmission Gate.   The important difference is that a 
transmission gate will pass the input regardless of its state, so L 
passes L, H passes H and Z passes as Z.   The disadvantage is that if 
you have a noisy signal, the TG doesn't clean it up at all the way a 
TB will.

The catch is that I cannot find one listed anywhere as a part that 
one can actually buy.  Are transmission gates purchasable parts?  Or 
are they just something they discussed in my VLSI textbook?

If they are real parts, would someone please suggest a part number? 
Preferably an octal transmission gate (eight on a chip) divided into 
two sets of four with separate control lines (OE) and one OE active 
low and the other active high.   That's how the SN74ABT241A tristate 
buffer is configured and it's perfect for my application, other than 
the little detail that a tristate buffer doesn't quite meet my needs. 

Since someone asked, a quick synopsys of my project (for those who 
missed the earlier threads) is that I'm trying to build 16 MB SIMMs 
for the Mac IIfx (1991) using 16M X 4 parts (Samsung KM44C16100).

The IIfx used unusual 64 pin SIMMs which are 8 bits wide, but keep 
the Data In and Data Out pins separate.  This is fine, when one is 
using X 1 DRAM chips, as X 1 chips have separate Din and Dout (D & Q) 
pins.   I've checked the IIfx motherboard and it actually does make 
use of the divided data pins to allow it to buffer writes, so I can't 
just tie the pins together.   If I tie the pins together, the data 
for buffered writes will go out on the machine's data bus, when it 
should just stay between the buffers and the SIMMs.

Using a (one per memory chip) SN74ABT241A, I can buffer the DRAM chip 
data pins and make them look like separate in and out pins.  The 
SN74ABT241A is an octal tristate buffer with two OE lines.  Each OE 
controls four of the buffers, and one is active high, the other 
active low.

So, using WE to control both OE lines of the SN74ABT241A means that 
the buffers will only conduct data from the Din SIMM pins to the DRAM 
data pins, when WE is low, and will only conduct data from the DRAM 
data pins to the Dout SIMM pins when WE is high.   There's no way for 
data from the SIMM's Din pins to feed back onto the SIMM's Dout pins.

This looks beautiful until one considers what happens when the 
computer is trying to use the data bus for other things.   If the 
computer leaves WE high, then the buffers will be driving some signal 
onto the Dout pins of the SIMMs.  With normal SIMMs this would be 
okay, because the Dout of the DRAM chips should go to High-Z after 
CAS goes high at the end of the Read, even if WE is still high 
(according to DRAM datasheets).

But in my situation, CAS goes high, the DRAM chip data pins go 
high-Z, and if WE stays high, then the buffer takes that high-Z input 
and tries to make it into some deterministic H or L output.  I need 
that high-Z output from the DRAM chips to propagate through the 

Or I can shut the buffer output down after CAS goes high.   So an 
alternative is to use an inverter and AND gate to deliver (CAS' AND 
WE) to the buffer control line for Data_Out.   This will probably 
work--barring timing issues--but involves two more components (or 
four if I don't want to run a trace cross-board), and the associated 
additional layout headaches.

I've actually already laid out the board (in software) with the 
inverter and AND gate added, but a transmission gate would be more 
elegant and keep the component count down.

But if there aren't actual transmission gate components available, 
I'll just produce a set of boards with traces and positions for the 
AND gate and inverter, and Vias in close proximity so I can do a bit 
of wire wrap modification and experimentation on the first set to see 
what control to the tristate buffer works--or doesn't work.

Jeff Walther

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