PDP-8 /e/f/m memory
ethan.dicks at gmail.com
Mon Aug 14 23:45:40 CDT 2006
On 8/15/06, C. H. Dickman <chd_1 at nktelco.net> wrote:
> Ethan Dicks wrote:
> > Why not use a pair of 62256s? 32Kx16 and ignore 4 bits. It'd even be
> > easy to use a Dallas DS1210 or something like it to provide battery
> > backup.
> I had the same idea back in December of '98.
> I was just looking over my notes, which are not as clear as they should
> be, but I'll give a try at converting them to a schematic. Here is a
> summary though:
> Two 62256 low power SRAMs with 4 bits ignored. The MA bus is buffered
> and inverted with 74HCT14s. The MD bus transceiver consists of more
> 74HCT14s, 74LS240 tri-state buffers and 74LS01s OC drivers, all wired
> together as sort of a DEC005.
OK. Is a DEC005 OMNIBUS-friendly? We used them on our Qbus COMBOARD,
so that's the context I think of them in.
> In retrospect, the 74LS01s are probably a bit weak for this purpose and
> the 74HCT14s might not have the ideal threshold.
Perhaps. Sorted and rebadged TTL 7401s _are_ OMNIBUS-friendly, aren't they?
> The control logic is trivial. The SRAM /CS is effectively grounded. /OE
> is controlled by MD DIR L. /WE is INHIBIT H NANDed with /OE. Note that
> just like core, the memory is written after every read.
OK... I thought the core stack handled re-writes, not the CPU...
perhaps I don't understand that part of the machine (never having had
to fiddle with it in depth).
> I complicated things a bit because I wanted to have the 3 core fields
> installed and have the rest semiconductor memory so there are switches
> that de-assert /CS when accessing fields 0, 1, or 2. I also have a write
> protect for field 7 so there is a switch that prevents asserting /WE
> when accessing field 7. I used this for storing a boot loader.
That's a reasonable feature. No reason to throw out real core if it
can be used in concert with a MOS board.
> The battery backup circuit is bit complicated with lots of 1N914 diodes.
> I was worried about standby leakage. I even used a reed relay to
> interrupt /CS on loss of POWER OK H. It seems to have worked though
> because I am still using the same 3.6V lithium battery after almost 9 years.
The Dallas DS1210 handles all of that in an 8-pin DIP, including
blocking /CS on power-down. It's a trivial circuit to implement...
just wedge the DS1210 between Vcc coming onto the board and the SRAM,
attach battery power to the DS1210. The only other attachment is the
/CS pass-through, IIRC. One can even design in the DS1210 and install
power and /CS jumpers across the socket if you don't happen to have
the chip handy (or don't care about BBU).
More information about the cctech