USR quad modems... (ontopic - really!)
Don
THX1138 at dakotacom.net
Wed Aug 16 17:48:43 CDT 2006
Tony Duell wrote:
>>> a TI/USR DSP chip, which is prolly useless outside of the intended use
>> Some of the DSP's are "general purpose" -- external program
>> store. However, since you called it a "TI/USR" part, I assume
>> it has a USR house number on it and, as such, is probably
>> a masked part. If so, "useless outside of the intended use" :>
>
> Unless either (a) the USB part number is just their code for a standard
> device (HP were fond of doing this...), or (b) you can disable the
> internal mask ROM and run it from external program store, say by changing
> the state of a pin.
>
> Without knowing more about the device I can't possibly know if either of
> these is the case.
TI realized early on that to make the DSP more ubiquitous, they
needed to suppport masked parts. Particularly for this sort of
application. I would suspect this is a low end 32010-ish part (?)
>>> So, *if* I can get a Dynamic-RAM -> Static RAM converter board designed
>>> for the CoCo, I could upgrade 4 CoCo3s to 512K with each modem board.
>> What's the issue *preventing* this from happening?
>> (unfamiliar with the internals of a CoCo3)
>
> The CoCo 3 is designed round a custom chip called GIME (Graphics,
> Interrupts, Memroy Enhancement). It handles all the video side, the
> memory mamangement (remmber the 6809 can only directly address 64K), etc.
> Said chip outputs a 9 bit multiplexed address (designed to link to the 9
> addres pins on 256K bit DRAMs), and the DRAM timing signals. It also
> expects 16 bit wide memory IIRC.
Ah, OK.
> It's probably possible to add external circuitry to turn that back into a
> normal 18 bit address and hang SRAM off it, but I think it's more work
> than finding some 41256s...
I would assume the controller would exploit page mode references
(especially when dealing with sequential accesses like video).
If so, this muddies any attempt to convert multiplexed
addresses back to a form suitable for SRAM (unless you use
SRAMs that also support page mode access!)
Yes, assuming it produces an 18bit (9R+9C) address, 41256's
would be the right way to go.
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