Build your own Apollo Guidance Computer

William Donzelli wdonzelli at
Wed Dec 20 23:03:56 CST 2006

> Seymour Cray did not like to use clocks.  For example, his designs call for
> all the outputs of an adder to be perfectly aligned.  He also did not like
> carry propagation, and wanted all the carrys out at the same time as the
> data.  I've never seen LSI that could achieve this on 64 bit operands.
> Compare the speeds of some of his arithemetic units, especially the parallel
> multipliers, to LSI contemporary to his design.

Yes, I can understand that the off the shelf ECL adders would not work
for his designs, but what about using the MSI chips? I bet if you
looked at his adder, all you would see would be a bunch of OR/NORs.
Stack the OR/NORs up, and you get AND/OR/INVERT gates. Certainly his
chip guys could have come up with a few flavors of AOI gates
(apparently they could make JK flip flops) to play with, and things
would go faster. No clocks involved. Same with demuxes - stack a bunch
of OR/NORs into AOIs, then stack those and you can get demuxes and
muxes, and clocking is still not an issue.

I can not get to my databooks now, but to use the 100K analogy, you
could make a faster adder if you had 100101, 100102, 100117s and
100118s to play with, instead of just 100101s and 100102s.  Sure, you
would have some unused inputs - ECL does not care. The board would
also be smaller, and probably use less power.

> But the switching time of even one gate is longer than the 2 inches of foil.

Yes, but if you do not have the delay of the foil because it "goes
away" inside a complex logic function on a chip, great - more room to
work with...

> His designs actually use the layout to deskew circuits.

...and if you do have to deskew, now you have the room to do it.  If
you eat propagation delays using individual gates, you have no room to
play with.

> When he left CDC, he looked at commercial logic families.  And I believe he
> did do a design with MECL III.

What design was that? Do you know why he did not stick with it? MECL
III was often rather difficult to deal with - but all ECL was until

> At the time of the 6600, 7600 and Cray 1, there was no commercial family
> that could equal the speed of the Cray designs.

What were the specs for the ECL used in the Cray-1? I have always
understood them to be somewhat close to what MECL III or 100K offered
- roughly 1 ns for a simple gate.

>  Some came along (10K/100K)
> but they were real power hogs.

Comes with the territory.

>  Every gate had complimentary outputs.

Most ECL guys I know of actually liked this feature. Gets rid of the NOTs.

>  Every
> signal had to be terminated.

Yes, but ECL does this correctly. At these speeds, if transmission
lines are not used, trouble is sure to follow.

> I spent 4 year designing with MECL 10K.  The experience was enough to
> convince to get out of design and go back to the field.  It was a miserable
> family to work with.  And I can assure you that there was skew on the
> outputs of any of the LSI blocks, but really bad on the 10181.

I have never heard anyone say much nice about 10K. It seems that most
guys much prefer the latter 10KH and 100K, mostly due to better
stability with voltage and temperature swings. 100K also was much
better at getting skew problems solved.

Will, who looked at 10G for a minute, then ran away.

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