large data transfert (write) to SDRAM at fixed frequency

[Pierre-Marie BOYER]

Le Dimanche 30 Juillet 2006 18:19, jim stephens a écrit :
> Pierre-Marie BOYER wrote:
> 
> >Hi !
> >
> >The ADC send data to the SDRAM through the DMA at a fixed rate during
> >may be 1 or 2 second, and is this process
> >can be stopped/disturbed by the internal refresh process of SDRAM ?
> >
> >If yes, is there a solution, to manage the two process ( fixed
> >acquisition and SDRAM refresh cycle) ?
> >
> >Thank you very much.
> >
> >  
> >
> If you are only collecting ADC data at that rate, can you use an I/O mapped
> device instead of DMA, and just poll and read the data?  Or are you saying
> that the ADC data will start up and run at some rate approaching the memory
> cycle time for 1 to 2 seconds?
> 
 No, ADC data run at a fixed frequency (30 MHz) during several seconds,
so data, from the ADC, must be writen to the sdram at rate one byte every 0,03 usec,
during several seconds.
( ADC hasn't buffer).
But what happend when the SDRAM enter in its refresh cycle, which occurs every 64ms ?

Tanks 

P.M.B.