Somewhat OT: FPGA Develpment Kits

Vincent Slyngstad vrs at
Wed Nov 22 09:04:06 CST 2006

From: "Ray Arachelian" <ray at>
> Vincent Slyngstad wrote:
>> I have some Perl that I wrote which will transform a netlist of
>> drawings based on the common DEC Mxxx modules into VHDL (generating
>> comments for the stuff left out).  Basically it has canned VHDL for
>> various modules that it instantiates based on the connections to the
>> module.  I used it to do some VHDL for a TC08.  (Unfortunately I can't
>> find a device with enough pins to handle the result :-).)
> Any chance you could use two devices?  I suppose you'd have to find a
> way to split the gates between them and then still interconnect them but
> have enough pins left over for actually interfacing with the original
> hardware.

It shouldn't be too hard to split the VHDL into components, if 
a reasonable functional partition can be decided upon.

For the TC08 and similar devices, the issue really comes down to 
the Posibus interface and the Blinkenlights.  Both are key features 
of the TC08, and both are very pin-hungry.  The dectape interface 
is not that many pins :-).

>> Of course, first you have to create the machine readable netlist for
>> the vintage gear, write VHDL for the various modules, etc. etc.
> Is there an open source VHDL compiler (or whatever the tool is) to turn
> the results of the VHDL into something that can be burned into the
> FPGA?  I'm curious about the process since I've never built anything
> along these lines.

I'm just using the free Xilinx tools.  They're not open source, but 
they are free-as-in-beer.

>> The original suggestion I made was for the 6100 or 6120 cpu-on-a-chip.
>> I'm not aware of any schematic for that.  As someone suggested, you'd
>> have to work from the data sheet.
> Which would mean that you actually have an emulator of those CPU's
> instead of a nearly identical part.  That's not necessarily bad, except
> that there may be subtle bugs that may creep in due to misunderstandings
> or undocumented opcodes, etc.

Sure.  Though you can revise the FPGA to fix bugs as they are discovered, 
and can make the timing as accurate as you like.

Or even fix lameness in the original, if one were so inclined.  That gets 
away from the original mission of restoring vintage hardware, but it would 
certainly make my SBC6120 more fun, and still potentially save some 
Decmates :-).

(One of my peeves with the 6120 is that they broke time-sharing.  So I 
actually like the idea of a 6100 with an external MMU better :-).) 


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