Open-source floppy reader: the data separator/sync-er works!
classiccmp at philpem.me.uk
Mon Apr 9 18:13:32 CDT 2007
I've got the first stage of my floppy disc reader working! Meaning, the
data separator and synchroniser works - I have a circuit that outputs a pulse
whenever the MFM 'magic sync sequence' (0x4489) is detected. In theory, I can
use that to sync the reader against sector boundaries on IBM-format discs, or
track boundaries on Amiga discs.
The data separator is an Verilog HDL reimplementation of the data separator
used in Petr Simandl's Sinclair Spectrum +2A floppy disc controller
(<http://www.simandl.cz/stranky/zxs/obrazky/zx_radic_89k.jpg>, but there's a
better quality schematic at <http://www.worldofspectrum.org/BackToThePlus3/>).
I'm driving the whole thing off a 32MHz TTL oscillator, divided down to 16MHz
for 3.5" DSHD, and 8MHz for 3.5" DSDD. I haven't tried FM encoded data yet,
though I have no reason to suspect it won't work, as long as I can figure out
what the clock divider needs to be set to.
I'm seriously miffed that I spent an afternoon trying to figure out why I
could get the separator to lock onto a DSDD disc but not a DSHD - seems most
of my DSHD discs are of marginal quality. The MPF920 in my desktop read them
fine, but the rather battered Panasonic JU-257A427P (complete with broken
drive door return spring) I was using with the FDR couldn't read them at all,
hence the huge number of SYNC pulses. Garbage in, garbage out.
I guess the next step is to do the RAM interface and bit timer, then the
MCU interface and firmware. The whole thing is currently squashed into a
Xilinx XC9572XL 3.3V CPLD, with a little room to spare for the acquisition
circuitry. The data-separator and sync detector are only using 29 of the 72
available logic macrocells, so I've probably got enough room for a 16-bit RAM
address latch, with space to spare. Can't really tell until I start
implementing it though.
Current power consumption is roughly 5V at 325mA while reading, according
to the display on my bench PSU.
For anyone who cares, I've thrown a couple of screenshots from my logic
analyser on my website:
Main blog entry:
720k (250kbps) sync - with SYNC lagging by one DWIN transition:
1.44MB (500kbps) sync - revised sync logic - SYNC doesn't lag now:
If anyone wants to see the (messy) Verilog code I've got at the moment,
contact me off-list and I'll send you a copy. It's probably very badly
written, but it works.
The tool I used to grab the screenshots from the analyser (a HP 1651B) is
also due to go online 'at some point' (read: when I can be bothered to fix
some of the bugs)... It basically emulates a HP Thinkjet and converts the
graphics output into a .BMP file, which is then converted to a PNG with
Irfanview and PNGOUT.
If and when this project gets a bit further off the ground, I plan to set
up another mailing list to handle discussions related to the disc reader --
for now, though, I think it's probably best to keep the discussions on the
For anyone that cares, I'll be posting announcements on the 'floppy-reader'
mailing list on my server
It's open-access, so anyone that feels like commenting is welcome to do so.
Phil. | (\_/) This is Bunny. Copy and paste Bunny
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