trixter at oldskool.org
Wed Aug 1 18:56:33 CDT 2007
Chuck Guzis wrote:
> On 30 Jul 2007 at 14:33, Jim Leonard wrote:
>> I've never heard of this. Are you talking about monitoring a bit in
>> the 8253?
> Bit 4, port 61h. You can use a simple toggle test to see if it's
> there, but on just about every system I've ever seen, it is. One of
> the holdovers from the PC-AT architecture.
I was confused because I always thought this was the speaker read gate.
It seems we are both right (the AT and later works as you describe;
the PC/XT bits in that location are a speaker read latch). Here is some
information paraphrased from the PC Timing FAQ:
Bit 4 of Port B at I/O address 61 hex on an AT and later machine is a
read-only bit carrying a signal called Refresh Detect. This signal comes
from a 'T' (toggle) flip-flop which is clocked by the refresh trigger
signal, which comes from CTC channel one. Assuming that the RAM refresh
rate has not been changed, this bit will toggle (change from 0 to 1 or
from 1 to 0) once every 15.0857 microseconds (the exact value is
216/14.31818), and Port B can be polled in a loop to implement a delay
of any length. For short delays, with interrupts locked out, this gives
an accurate and very convenient relative delay mechanism. However, for
long delays, it would be naughty to leave interrupts locked out for the
entire delay period, and interrupts will cause gaps in the polling
process, slightly lengthening the delay (it will wait longer than expected).
There are several caveats. This method will not work on PCs and XTs.
Also it will not work in an environment where Port B is emulated (for
example, under OS/2 and probably any other virtual DOS machine). If the
DRAM refresh period has been changed, the timing will be changed
proportionately. Finally, Microchannel PS/2 architecture may not
emulate this bit properly due to the level triggering they use.
Jim Leonard (trixter at oldskool.org) http://www.oldskool.org/
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