DRAM camera sensor
JeLynch at stny.rr.com
Sat Jun 2 09:01:54 CDT 2007
Phase I (simple B&W):
I used a Z-100 computer with a TI 256K DRAM (512 x 512). The video
chip in the z-100 could be configured for 640 x 512 and the DRAM
imager replaced one DRAM chip (ES) and was on a 1 foot tender (which
is about the functional limit). Using a simple assembly code to read
the DRAM transform the logic address to physical topology.
Phase II (gray scale): more complex, used a memory board and replaced
DRAM to a DRAM on tender. Programmed the DRAM controller for various
refresh rates (soak time). Of course the other "bits" on the memory
board were rendered useless.
TI (and others) would publish a memory map to help with the topology
decoding. Of course it did not directly address redundant bit lines.
At 10:34 PM 6/1/2007, you wrote:
> > There was at least one UK computer magazine which carried such
> >a project too - unfortunately I can't remember which one, let
> >alone which year :-(
>I vaguely remember "Practical Electronics" (could have been "ETI",
>but I don't think so) carrying some sort of digital camera project
>around about 1980/81(ish), but I have a feeling it was based on a
>CCD sensor; IIRC the accompanying article mentioned being able to
>use expoded DRAMs as image sensors (the first time I became aware of this).
> TTFN - Pete.
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