brad at heeltoe.com
Wed Jun 20 20:18:42 CDT 2007
Guy Sotomayor wrote:
>I hope so because this is going to be a lot of work. :-) Not only do I
>have to do the hardware design (and fab) but also have to write the
>verilog for the FPGA and a resonable amount of code on the uC.
It wasn't that hard for unibus. I don't know much about massbus,
however, that might be a lot harder (no doubt).
My first cpld version had the cpu doing all the work and that put a big
load on the cpu; but it does do dma in both directions and can generate
interrupts. I got it to boot rt-11 via a simulated rl02.
I've since redesigned the cpld to take some load off the cpu. But work
has gotten in the way of progress. It is nice to use a cf disk,
however, as a backing store. very simple and easy to update. I just
made a simple 4 layer quad width board; I used a split power plane with
half the board at 5v and half at 3.3v; the cpld I used has 5v tolerant
i/o. for the cpu I used an atmel sam7s, which is my current favorite
I hope to get back to it this summer.
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