Core duo SC/MP?

Holger Veit holger.veit at iais.fraunhofer.de
Mon Oct 1 21:04:58 CDT 2007


Tony Duell said:
>>
>> Hi there folks.  I just got a sweet NS LCDS (low cost dev system) with
>> a SC/MP II processor card and nice set of docs on the chip itself, the
>> lcds,appnotes,and assembly programming    It looks pretty easy to add
>> more than one scamp to the same bus and I was wondering if there are
>
> I rememebr an article in 'Computing Today' magazine _many_ years ago, I
> would guess around 1980. It was to add a second SC/MP to the Science of
> Cambridge MK14, so that you could, for example, run the monitor program
> on one chip and a user program on the other.
>
>>From what I remember, you ended up soldering the 2 SC/MP on top of each
> other with a couple of pins bent out and not directly conencted. There
> was a bit of scrossed-over wiring to get the arbitration chain right, and
> a swich to disable the second processor wired to on of the pins. That was
> about it. No otehr chips were involved.

The actual daisy-chaining scheme to be used to run multiple SC/MPs is
described in the datasheet. Basically this infact results in piggybacking
the two CPUs with the exception of NENIN/NENOUT pins. This is in principle
not limited to two CPUs. You could build a small tower of CPU chips this
way; however, with N chips, each of them will only run at one Nth of the
central clock speed. And the SC/MP does not belong to the fastest 8 bit
CPUs ever.

There is one further problem with real multitasking this way, though. The
CT article hacks it by simply switching one of the two CPUs off, and then
uses the same memory. The problem is to have each CPU identify itself and
have it run different code from boot up. In the naive solution both CPUs
would, after reset, run the same monitor code which won't work. The better
method is not to tie NRDS/NWDS (the memory read/write lines) together, but
connect them to different memory chips - in this case ROMs, so one could
become the master, and the others the slaves. Another idea is to add an
offset to the upper four address lines to have each chip operate in a
different 4k bank
(just use 7483 adders there). This is accomplished easily because with the
8050/8060 (the 807x "SC/MP III" was constructed better) the upper 4 bits
are multiplexed through the databus during NADS time, and you need some
glue logic latch anyway to expand the address space beyond 4K.

To the original poster: can you scan your papers and make them available
to Al Kossov? Since National seemed to have thrown away all old original
documents of that time, such documentation is rather rare and interesting
to be conserved.

-- 
Holger



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