PDP-8 on FPGA project & where is Hans Pufal?

[Peter C. Wallace]

On Fri, 19 Dec 2008, der Mouse wrote:

> Date: Fri, 19 Dec 2008 10:53:46 -0500 (EST)
> From: der Mouse <mouse at Rodents-Montreal.ORG>
> Reply-To: "General Discussion: On-Topic and Off-Topic Posts"
>     <cctalk at classiccmp.org>
> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org>
> Subject: Re: PDP-8 on FPGA project &  where is Hans Pufal?
> 
>> Yes, but the goal is to minimize warnings (haha!).....
>
> Funny, I'd've thought the goal would be to have a working circuit.  If
> minimizing warnings really is your goal, there's a very easy fix.
>
>> Your code above does not result in latches.  It results in D type
>> flipflops!
>
> What's the difference?  As I've learned to use the words, D-flops _are_
> latches.  Have I mislearnt?



Yes, a D FF is a _clocked_ latch

Its easy to create (non-clocked) latches in VHDL inadvertently.
These result in _important_ warnings...

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Peter Wallace
Mesa Electronics

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