[personal] Re: PDP-8 on FPGA project & where is Hans Pufal?

bfranchuk at jetnet.ab.ca bfranchuk at jetnet.ab.ca
Tue Dec 23 19:30:10 CST 2008


Roy J. Tellason wrote:
> On Monday 22 December 2008 04:07:10 am Mike Hatch wrote:
>>> A simple example of the differnce. If you take a D-type flip-flop and
>>> connect the output to a NOT gate and the output of that back to the D
>>> input, then you get a divide-by-2-circuit. Feed in a regular clock at one
>>> frequency and the Q output will toggle at half that frequency. But if you
>> A clocked JK with the JK held high will perform the same function.
> 
> As will tying the D input back to not-Q,  which most of them have.  The 
> advantage to using the D-type over the J-K is two fewer package pins needed,  
> which may or may not be important to somebody.
> 
> And what the heck does that J-K stand for,  anyway?

J(am) and K(lear) ?

BTW  Lets not forget the early computers used pulses not logic levels.
That was fun timing !



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