68k homebuilts

[Peter C. Wallace]

On Fri, 12 Dec 2008, Chuck Guzis wrote:

> Date: Fri, 12 Dec 2008 12:29:26 -0800
> From: Chuck Guzis <cclist at sydex.com>
> Reply-To: "General Discussion: On-Topic and Off-Topic Posts"
>     <cctalk at classiccmp.org>
> To: "General Discussion: On-Topic and Off-Topic Posts" <cctalk at classiccmp.org>
> Subject: Re: 68k homebuilts
> 
> On 12 Dec 2008 at 10:47, bfranchuk at jetnet.ab.ca wrote:
>
>> Most of the FPGA  designs I have seen are RISC's or some 6502 offshoot.
>> I am sticking for now to CPLD's, since you don't have to configure the chip
>> like a FPGA, Also a little cheaper if you stick to a bare design like a
>> PDP8.
>> Two CPLD's for the data path and 1 CPLD for control.
>
> How about a 20-bit word size, 4 bit opcode, 65KW addressing space,
> simple one-address+accumulator machine?  Enough directly-addressable
> memory to do just about whatever you need to do, simple to implement.
>
> Cheers,
> Chuck

Very similar to what we use for embeddded 8,16,32 bit CPUs in FPGAs. For I/O 
(well memory) intensive operations, the accumulator oriented architecture 
beats the socks off of RISCy designs with only memory load and store (that are 
basically designed for systems with large slow memory instead of small fast 
memory)

>

Peter Wallace
Mesa Electronics

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