cctalk Digest, Vol 54, Issue 62

[Chuck Guzis]

On 28 Feb 2008 at 10:19, Geoffrey Bunza wrote:

> On the note of the CDC 6600 machines, et al., There was a peripheral
> processor which was used to boot the mainframe, and it had many rows of
> toggle switches, in groups of 18 or 36 if I remember right, which
> either contained the boot code or controlled the boot. The peripheral
> processor was a computer in its own right by any standards. 

Well, actually a tenth of a computer.  The basic cycle time of the 
mainframe was 100 nsec.  There were 10 PPUs in a standard 
configuration, with a cycle time of 1 usec.  In other words, each PPU 
was little more than 4K of 12 bit core, a P-counter and an 18-bit 
accumulator (that's over-simplifying things a bit, but it'll give you 
the idea).  The "guts" (instruction decode and execution) was time-
sliced around the 10 PPUs.  This was sometimes referred to as the 
PPU's slot "in the barrel".  All I/O channels were accessible from 
any PPU and any PPU could access central memory.  So, if a driver or 
bit of hardware malfunctioned, the PPU might hang, but the system 
could keep on running.  Similarly, if a PPU was hung on an empty 
channel, it was often possible to break it loose from the operator's 
console.

The deadstart panel itself was a 12x12 matrix of switches (12 words 
of 12 bits).  There were some other switches controlling diagnostic 
mode, and control of various options (e.g. CEJ/MEJ); many systems had 
a key-operated switch which could disable the deadstart panel to keep 
rogue programmers from sneaking time on the system. :)

Deadstart was quite simple.  Each PPU had its P-counter forced to 
0000 and a block input instruction from the channel corresponding to 
the position of the PPU in the barrel.  (i.e., 0-9).  The contents of 
the deadstart panel switches were output to channel 0 after an 
initial word of zero and the channel disconnected.  PPU 0 then began 
executing at location 1 and could then proceed to read the remainder 
of the OS bootstrap and transmit resident programs to each of the 
other PPUs.  No blinkenlights and no ROM involved at all--either the 
system started or you had blank screens staring back at you.  Time to 
get out the scope...

10 is a magic number for the 6600.  Memory is interleaved 10-way, 
there are 10 PPUs, 10 characters per CPU word, 10 functional units...

Later implementations of the architecture dropped the idea of the 
barrel and provided a complete processor for each PPU.

Cheers,
Chuck