8-bit micro MMU's

[Dave McGuire]

On Jan 28, 2008, at 3:02 PM, Chuck Guzis wrote:
> With the slow memory chips back then, making things work with the
> wretched 8202 DRAM controller was a real chore.  I seem to recall
> that if you  ran worst-case numbers, you could wind up with the
> requirement of a negative access time for the DRAM for a 5MHz 8085.
> Adding bank-mapping hardware in the address path didn't improve
> things any.

   A slight diversion here...What is wretched about the 8202?  I ask  
because I got ahold of a few not long ago (and some 8203s) and was  
considering putting something together with them to play with.

   I worked with the 8207 DRAM controller extensively on the Navier- 
Stokes Supercomputer Project at Princeton in the mid-late 1980s...We  
had lots of problems with the memory arrays at first, but they were  
eventually all traced to power...both nasty spikes on Vdd and ground  
bounce.

            -Dave

-- 
Dave McGuire
Port Charlotte, FL